SA-110: The Pioneer of the StrongARM Microprocessor Family
The SA-110 marked a significant milestone as the first microprocessor in the StrongARM family. Launched in 1996, it quickly established itself as a powerhouse for portable devices, internet/intranet appliances, and thin client systems. By combining high performance with power efficiency, the SA-110 paved the way for a new generation of mobile computing.
The chip was developed under the leadership of designers Daniel W. Dobberpuhl, Gregory W. Hoeppner, Liam Madden, and Richard T. Witek. Its versatility led to early adoption in high-profile hardware, including the Apple MessagePad 2000, the Acorn Computers Risc PC, and the Eidos Optima video editing system.
[ไม่มีภาพประกอบ]Key Facts
- Launch Date: First versions announced February 5, 1996.
- Clock Speeds: Ranged from 100 MHz to 233 MHz.
- Transistor Count: 2.5 million transistors.
- Manufacturing Process: DEC's proprietary 0.35 μm CMOS-6 process.
- Die Size: 7.8 mm by 6.4 mm (49.92 mm²).
- Package: 144-pin thin quad flat pack (TQFP).
Technical Architecture
The SA-110 utilized a scalar design, meaning it processed one instruction per clock cycle. It employed a classic five-stage RISC (Reduced Instruction Set Computer) pipeline, which executes instructions in-order to maintain simplicity and efficiency.
Pipeline Stages and Functional Blocks
The microprocessor was divided into several specialized blocks to handle different stages of execution:
- IBOX: Handles the first two stages of the pipeline. It manages the program counter, fetches instructions, and decodes complex ARM instructions into simpler sequences. It also processes branch instructions without the use of branch prediction hardware.
- EBOX: Where execution begins at stage three. This block contains the register file (featuring three read and two write ports), the arithmetic logic unit (ALU), a barrel shifter, a multiplier, and condition code logic. While the ALU and barrel shifter operate in a single cycle, the multiplier is non-pipelined and requires multiple cycles.
- MMUs (IMMU and DMMU): The Instruction Memory Management Unit and Data Memory Management Unit each feature a 32-entry fully associative translation lookaside buffer (TLB), supporting page maps of 4 KB, 64 KB, or 1 MB.
- BIU and WB: The Bus Interface Unit (BIU) manages external communication, while the Write Buffer (WB) uses eight 16-byte entries to enable the pipelining of store operations.
- PLL: The Phase-Locked Loop (PLL), contracted to the Centre Suisse d'Electronique et de Microtechnique (CSEM), generates the internal clock from an external 3.68 MHz signal.
Memory and Cache System
To compensate for the use of slow, low-cost external memory, the SA-110 featured robust caching. It included separate 16 KB instruction and data caches, both of which were 32-way set-associative and virtually addressed. This high associativity improved hit rates, while virtual addressing allowed memory to be cached and uncached simultaneously. These caches were the most transistor-heavy components, occupying half of the total die area.
[ไม่มีภาพประกอบ]Manufacturing and Specifications
The SA-110 was fabricated by DEC at its Fab 6 facility in Hudson, Massachusetts, using the CMOS-6 (complementary metal-oxide-semiconductor) process. This sixth-generation process featured a 0.35 μm feature size and a 0.25 μm effective channel length, utilizing three levels of aluminium interconnect.
One of the chip's most flexible features was its variable power supply, ranging from 1.2 to 2.2 volts. This allowed engineers to balance power consumption against performance, as higher voltages enabled higher clock rates.
| Feature | Specification |
|---|---|
| Clock Speeds | 100, 160, 200, 166, and 233 MHz |
| Transistor Count | 2.5 Million |
| Process Technology | 0.35 μm CMOS-6 |
| Cache Size | 16 KB Instruction / 16 KB Data |
| Operating Voltage | 1.2V to 2.2V |
| Die Dimensions | 7.8 mm x 6.4 mm |
Frequently Asked Questions
What was the first commercial product to use the SA-110?
The first design win for the SA-110 was the Apple MessagePad 2000.
How did the SA-110 handle complex ARM instructions?
The IBOX (Instruction Box) decoded complex instructions by translating them into sequences of simpler instructions during the second stage of the pipeline.
Why did the SA-110 use 32-way set-associative caches?
The high set associativity was designed to provide a higher hit rate, allowing the processor to perform efficiently even when paired with slow, low-cost memory.
Who designed the PLL for the SA-110?
The PLL was not designed by DEC; it was contracted to the Centre Suisse d'Electronique et de Microtechnique (CSEM) in Neuchâtel, Switzerland.
What was the purpose of the variable voltage power supply?
The variable voltage (1.2V to 2.2V) allowed designers to find an optimal balance between power consumption and performance, with higher voltages supporting faster clock rates.