Microwatt: A Compact Power ISA 3.0 Processor Core
In the landscape of open-source hardware, Microwatt stands out as a streamlined 64-bit scalar integer processor core. Designed to be efficient and compact, it implements a specific subset of the Power ISA 3.0 instruction set, providing a functional foundation for those working with the Power architecture in a minimal footprint.
Core Architecture and Specifications
Microwatt is built as a bi-endian processor, meaning it can handle data in both big-endian and little-endian formats. To manage its operations, the core utilizes 32 general-purpose registers and 32 floating-point registers, both of which are 64 bits in width. For communication with memory, the system employs the Wishbone interface, a standardized bus for interconnecting intellectual property cores.
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Development and Evolution
The initial phase of Microwatt's development was completed within a few months. This first iteration focused on the essential integer processing functionality required for basic compliance with the instruction set, notably omitting a floating-point unit and a Memory Management Unit (MMU)—the hardware component responsible for translating virtual addresses to physical addresses.
As the project matured, several critical enhancements were integrated to increase its utility and performance:
- Pipelining: Implementation of instruction pipelining to improve throughput.
- Memory Enhancements: The addition of a 16 KB instruction cache and a 32 KB data cache.
- Memory Management: Integration of a non-hypervisor-capable MMU.
- Extended Instructions: Support for divider instructions and floating-point operations.
- Debugging: Inclusion of a JTAG (Joint Test Action Group) debugger interface for hardware-level testing.
Technical Implementation
Microwatt is developed using VHDL 2008, a hardware description language used to model electronic systems. For verification and testing, the project relies on the GHDL simulation environment, ensuring the design behaves as expected before physical implementation.
| Feature | Specification |
|---|---|
| Architecture | Power ISA 3.0 (Subset) |
| Bit-width | 64-bit |
| Registers | 32 General Purpose / 32 Floating-Point (64-bit) |
| Memory Interface | Wishbone |
| Caches | 16 KB Instruction / 32 KB Data |
| HDL Language | VHDL 2008 |
Chiselwatt: The Scala-Based Alternative
Alongside Microwatt, a sibling project known as Chiselwatt exists. While it also implements the Power ISA 3.0 instruction set, it differs fundamentally in its construction. Instead of VHDL, Chiselwatt is written in Chisel, a hardware construction language embedded in Scala.
Key Facts
- Microwatt is a 64-bit bi-endian scalar integer processor.
- It implements a subset of the Power ISA 3.0 instruction set.
- The core features 32 general-purpose and 32 floating-point registers.
- It utilizes a 16 KB instruction cache and a 32 KB data cache.
- The design is written in VHDL 2008 and simulated via GHDL.
- Chiselwatt is a related project written in the Scala-based Chisel language.
Frequently Asked Questions
What is the primary purpose of Microwatt?
Microwatt serves as a tiny, open-source 64-bit processor core that implements a subset of the Power ISA 3.0 instruction set.
Does Microwatt support floating-point operations?
While the initial version did not include a floating-point unit, later additions to the implementation provided floating-point support and 32 dedicated 64-bit floating-point registers.
What is the difference between Microwatt and Chiselwatt?
The primary difference is the language used for development: Microwatt is written in VHDL 2008, whereas Chiselwatt is written in Chisel (based on Scala).
What memory interface does Microwatt use?
Microwatt uses the Wishbone interface for its memory communication.
Does Microwatt have a Memory Management Unit (MMU)?
Yes, a non-hypervisor-capable MMU was added to the implementation in later development stages.